الفهرس 
Chapter 1 IntroductionOnly 14 pages are availabe for public view
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Abstract
In a world where the demand for faster, better and more efficient electronic devices is ever-growing, it is no wonder that the semiconductor industry is constantly looking for ways to optimize the design cycle for such devices, to obtain better devices at lower costs.
To optimize this cycle, the process must be examined from several angles. Digital cir- cuits make up a large part of the integrated circuits within these advanced devices. The process of digital circuit design consists of two main parts, namely: the front-end design and the back-end design. The back-end design is concerned with processes such as syn- thesis, placement and routing and static timing analysis. The front-end design on the other hand, may also be broken down into two parts: the Register-Transaction Level (RTL) design, and the Design Verification. The RTL design process is concerned with designing synthesizable digital circuits using hardware description languages (HDL) such as: VHDL or Verilog, whereas the design verification process is concerned with verify- ing the functionality of the developed RTL design and ensuring that it can perform its desired functionality fully and without flaws.
A major part of design cycle time (70%) is reported to be consumed in verification activities. This is mainly due to the difficulty in obtaining functional coverage closure in a timely manner with a limited number of resources. Thus, the norm has shifted in verification from directed testing to constrained random verification and finally to cov- erage driven verification. The most recent advancement in the field of coverage driven verification is the incorporation of machine learning in the stimulus generation process. Most commonly in previous works: supervised learning and unsupervised learning have been investigated for this task. Reinforcement learning is the least investigated type of machine learning for this task. Additionally, previous works focus on coverage metrics and ignore metrics such as bug detection rate. Another important aspect that has not been investigated in the literature thoroughly is the task of training the RL agent effi- ciently and preventing it from falling into pit-falls as the design beign verified becomes more complex and thus the agent’s action space and observation space become more complex. Previous works also focus on simples designs like caches or small logic gates rather than dynamic systems with varying levels of complexity. This work aims to close the gaps mentioned above.
In this work, three different realistic RTL designs are designed with varying levels of complexity. A verification environment is designed with modular, reusable blocks that has been modified to each RTL design. Three different RL agents are selected and an RL environment is built that can interact with each of the three agents seamlessly. A tech- nique for the interaction between the RL environment and the verification environment has been developed. The full setup is then used to demonstrate the superior coverage
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closure capability of the RL based environment, Subsequently, the bug detection rate is introduced into the RL agents’ reward functions (it becomes a mutli objective function), and it is demonstrated how the RL agents are able to achieve both faster coverage closure and larger bug detection rate. Finally, a technique for efficiently training the RL agent and preventing it from pit-falls is developed and described and used to demonstrate its superior training performance versus the conventional training technique. The thesis is divided into five chapters, in addition to the list of figures, the list of tables, the list of abbreviations, the list of symbols and the bibliography as listed below:
Chapter 1 Provides an introduction for this work. First, it introduces the problem state- ment, then the motivations for the work in this thesis is described. Afterwards, the main research objectives and goals of the work are explained. Moreover, the design challenges and methodology of the work are listed. Finally, the thesis roadmap is provided.
Chapter 2 Presents the background on different aspects of the work. It contains a section that first describes the history and background of the functional verification of digital designs and its different phases, followed by a chapter that discussed the coverage metrics in digital design functional verification. Furthermore, it presents a section that discussed machine learning usage in EDA and in functional verification of digital designs. Finally, it ends with a chapter giving an overview or basic concepts of reinforcement learning. Chapter 3 Describes the work done in this thesis from multiple perspectives. It starts by introducing the mathematical descriptions of the three RL agents used in the course of this work. Then, the three RTL designs used in the application of this work are described in full detail. Afterwards, the verification environment with all its blocks and sub-blocks are described in detail, as well as the technique for the interaction between the python-based RL environment and SV-based verification environment. The special technique for training RL agents in large and complex action and observation spaces is also described in this chapter, as well as the metric of bug detection rate.
Chapter 4 Explains the final results and findings that have been generated form this work. Giving detailed comparisons between the coverage performance of different agents in different RTLs and using different testbenches. Comparisons are also held in terms of bug detection rate. The learning curves of different agents are also compared in case of conventional training technique and different versions of the new training technique proposed in this work.
Chapter 5 Constitutes the conclusions of this work by providing a brief summary of the work done and the results and finding reaches as well as suggesting future work based on these finding and outputs.