الفهرس 
AbstractOnly 14 pages are availabe for public view
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Abstract
In this thesis, many technqiues of the fault detection, diagnosing and automatic correction for digital systems have been examined due to the significane of these processes in digital control design. In order to avoid faults being discovered in the post-silicon stage, which is very expensive to fix, the stage of verification, fault detection, and rectification of errors in the pre-silicon stage has emerged as one of the most crucial stages of producing digital systems. Most fault detection algorithms can be solved by transformation to a satisfiability (SAT) problem decipherable using SAT solvers or by using machine learning and deep learning models. By focusing on three primary issues—increasing the scale of the systems, the quantity of potential faults, and the length of the error traces—different models of the error detection and correction process have therefore been proposed.
Firstly, three different algorithms of fault detection and diagnosing techniques are proposed. Two proposed methods based on MAX-SAT problem by minimal unsatisfiable subsets (MUS) computation which is an explanation of infeasibilities of the Conjunction Normal Form (CNF) formula equivalent to erroneous digital circuit. Also, the third proposed fault detection algorithm is based on deep learning for getting benefit of large amount of data by growing size of digital circuits.
Additionally, three different algorithms for auto-correction techniques are proposed. The first algorithm is called an automatic correction method (ACM) using an improved in-circuit mutation technique and improved parallel distribution of test patterns through the debugging circuit using Computer Unified Device Architecture (CUDA). The second algorithm is called enhanced automatic correction (EAC) algorithm. The improvements can be accomplished by sorting the design bugs and utilizing the solution of SAT engines for predicating the corrected gate without explicitly embedding look-up tables (LUTs) in the place of bug location. The third algorithm called automatic correction method with producing compact test vectors (ACM-CTV) is proposed for combining rectification with producing compact test patterns. In this algorithm, our goal is to avoid the dependency of given test patterns by incrementally generating compact test patterns corresponding to design errors during rectification. Also, the second goal is to reduce the size of in-circuit mutation circuit for error-fixing process. The experimental results prove that our proposed correction algorithm outperforms the previously published tools in terms of average speed.