الفهرس 
Error-Control CodingOnly 14 pages are availabe for public view
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Abstract
The Viterbi algorithm is a well-established technique for channel coding and equalization in high performance digital communication systems. The achievable speed of conventional Viterbi decoders is limited by the inherent non-linear add-compare-select (ACS) recursion. A high speed state-parallel VLS! architecture and low-power design methodology on the system-level are presented for the design of a systolic sliding block Viterbi decoder (SBVD) for code division multiple access (CDMA) digital cellular/personal communication services (PCS) applications. The interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow are particularly emphasized in this thesis.
For prototyping, a four-state, systolic SBVD was implemented. The implementation results of this new architecture display the reduction in both power consumption and area while still attaining the predetermined decode speed of 1.2 Gbps.