الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
Design verification is the prevailing cost in the product development process, it consumes nearly 70% of product design time and is considered the time-to-market bottleneck. Given the high cost of manufacturing of microchips, finding flaws after the production of system designs, would be very expensive. Design complexity has increased over the past few decades and there is evidence that the complexity will continue increasing in the upcoming years. More design complexity is associated with a complex, high cost and time-consuming development process.
It is essential to verify the design early in the development process for effective verification, so engineers can avoid iterations during the development cycle. High-level designs are described and verified using C/C++-based languages such as SystemC. SystemC extends the capability of C++ to model hardware/software designs, it adds important hardware concepts to C++ as concurrency, hardware data types, and timed events.
Universal verification methodology (UVM) is the standard and dominant industrial verification methodology for digital designs. It allows building reusable, configurable, modular, and scalable verification environment. UVM has made available recently in SystemC to bring all the advantages of UVM in SystemC. UVM-SystemC makes it possible for IC-verification engineers to reuse structured system level design verification environments.
The purpose of this thesis is to propose a methodology for creating a hardware-accelerated UVM-SystemC test environment that is interoperable and can be re-used on simulators, HW emulators, and FPGA prototyping systems without any change in the source code. In hardware-accelerated testbench, emulation is used to accelerate the simulation by running the Design Under Test (DUT) and the synthesizable part of the testbench on the emulator, while the synthesizable untimed part of testbench runs on the workstation. The proposed methodology in this thesis is demonstrated through two case studies: Advanced Encryption Standard (AES) core and Network on Chip (NoC) mesh.