الفهرس يوجد فقط 14 صفحة متاحة للعرض العام
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المستخلص
CMOS Integrated Circuits currently have very small geometrical features which lead to very high transistor density per chip. Consequently, a very important parameter in the design cycle is power consumption. With the proliferation of battery-operated devices, designing a circuit with low power consumption has become a must. In general, it is essential for a designer to use a CAD tool that can quickly and accurately predict the circuit{u201F}s power consumption. Existing CAD tools suffer from one main drawback, namely accuracy. This thesis aims at producing a CAD tool whose main advantage is accuracy. The technique used is the Logic Pictures (LPs). A Logic Picture is defined as the set of logic values at all gate outputs in the circuit for a given input vector. A deterministic and accurate method to calculate the nodes{u201F} toggle rate of CMOS logic circuit is presented. The nodes{u201F} toggle rate can be related directly to the dynamic power consumption of the circuit due to the charging and discharging of the load capacitances. The contributions of the thesis are the study of Logic Pictures in the context of combinational and sequential circuits. The unit-delay model is used first where the tool is applied to several standard/non-standard benchmark combinational circuits. The power consumption produced by the tool is compared to exhaustive simulations as well as Monte Carlo simulations. It is proven that the tool produces accurate results. The tool is then enhanced by using the real-delay model that closely matches the real-world circuits. Again, it was verified that it indeed produces accurate results