الفهرس 
Ultra low power sar adc for sensor nodes
SummaryOnly 14 pages are availabe for public view
 |  | from | 132 |  |  |
| | | from | 132 | | |
Abstract
A new charge redistribution technique for CDAC based SAR ADC, with an input dynamic range equals to twice the reference voltage for single ended applications. Compared to SAR converters using conventional switching techniques, the proposed solution reduces the capacitive digital-to-analog (CDAC) average switching energy and total capacitive area by 78.2% and 50%, respectively. Moreover, the Di{uFB00}erential Non-Linearity (DNL) and Integral Non-Linearity (INL) are improved by factor of two compared to the conventional approaches. A new two stages dynamic comparator architecture is introduced to minimize the hysteresis e{uFB00}ect and help in improving the overall linearity. A prototype was fabricated using TSMC 65nm CMOS technology and it occupies an active area of 0.039mm2. The ADC achieves an SNDR of 62dB for an input voltage amplitude of 1.5Vp and frequency of 100kHz. The ADC consumes 5uA at 1MS/s resulting in a {uFB01}gure of merit (FOM) of 11-fJ/conversion step