الفهرس 
Literature reviewOnly 14 pages are availabe for public view
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Abstract
Graphical processing units (GPUs) have wide variety of applications in different fields such as compute art, engineering, science, medicine, entertainment, advertising, visualization, military, and graphical user interface. The growth in the GPUs applications has led to evolution in the hardware design to handle the needed increase in performance. Also, the fast growth of the mobile electronics market and the transition from text based applications to versatile multimedia applications resulted in increasing the popularity of mobile communication devices. Real-time 3D graphics are becoming one of the greatest interesting applications in mobile workstations due to their benefits for gaming, advertising, marketing, and avatar. GPUs are mainly composed of several unified shaders. Each unified shader contains general purpose arithmetic unit and special function units (SFUs) that are used for computing special transcendental and algebraic functions not provided by the general function unit. Functions such as sine, cosine, reciprocal, logarithm, exponential, and compound functions are computed by SFUs. These functions use most of the clock cycles in the real time 3D graphics systems. As a result of that, they consume most of the computing power. Accordingly, reducing the power consumption of the arithmetic unit inside the programmable shaders is the main target for the optimization effort.
An energy efficient Double Logarithmic Arithmetic (DLA) technique is proposed for 3D graphics applications. DLA manipulates the logarithmic arithmetic and improves the architecture for the realization of the transcendental functions and the advanced lighting model using energy efficient techniques. The DLA features complete elimination of multipliers in logarithmic domain by using successive logarithmic converters. This work demonstrates up to 56% reduction in power consumption as compared to the existing techniques. The main advantage of this approach is the ability to perform the complex functions using power-efficient, area-efficient, as well as high frequency design. The proposed technique performs transcendental functions using the multiplier free hardware architecture. Moreover, based on non-uniform subdivisions and piecewise linear approximation, novel logarithmic and antilogarithmic converters are also proposed. These converters achieve optimal power consumption as compared to several recent approaches. They provide low relative error with less non-uniform subdivisions. Up to 19%, 12%, and 20% reduction in relative error, area, and power consumption, are achieved, respectively.
In addition, a dual channel multiplier (DCM) for energy efficient second order piecewise-polynomial function evaluation for 3D graphics applications is proposed. The performance of the evaluation process is hig
A novel hardware implementation for polynomial evaluation is presented. The proposed approach compensates the complex multipliers by using DCM which reduces the hardware complexity. The DCM scheme performs complex functions with power-efficient and area-efficient approaches. The multiplier reduces the hardware computational effort in the piecewise polynomial approximation with uniform or non-uniform segmentation. For large operand input size, multiplier adder converter (MAC) and a dedicated radix4 squaring unit are also proposed. These units achieve the least power consumption as compared to previous approaches with large input word size. Comparison with general-purpose multiplication has shown reduction in power, and delay by up to 36%, and 50%, respectively. The proposed technique exhibits up to 93% saving in power consumption as compared to the current traditional schemes. This thesis presents novel designs of low power and low complexity arithmetic unit for GPU. The proposed arithmetic units suitable for low-power 3D graphics applications.