الفهرس 
Substrate Integrated Waveguide (SIW)Only 14 pages are availabe for public view
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Abstract
Substrate Integrated Waveguide (SIW) power dividers/combiners play an important role in modern 5G communication systems and millimetric wave applications. This thesis presents the development of SIW transmission lines using double via rows configuration to improve its power handling capability, operational bandwidth and to reduce its radiation loss. A model to calculate the effective width in double via row (DVR) structures is presented based on transmission line theory. Moreover, a graphical user interface (GUI) calculator program using MATLAB is proposed to help the designer to calculate SIW electrical parameters and obtain generalized design curves. The proposed model is verified through parametric analysis, fabrication and measurement of case studies using various design parameters. It is concluded that the best configuration using DVR SIW structure by using separation between vias equals to two times the via diameter and the distance between the parallel rows equals to three times the via diameter. The fabricated structure achieves 40% enhancement in insertion loss and 31.32% wider bandwidth and 42.85 % lower radiation loss compared to SIW structures utilizing single via row (SVR) configuration. A high-power measurement setup is applied to predict the power handling capability of the proposed structure.
The proposed structure based on the preferred design parameters is used to design SIW/HMSIW power divider/combiner with improved bandwidth and enhanced power handling capability. The fabricated DVR SIW/HMSIW power divider/combiner features good input/output matching, insertion losses and isolation between output ports. All measurements agree well with 3D EM simulations which verifies the proposed technique. Finally, the proposed DVR SIW achieves 16% smaller size, 30% wider bandwidth and better S-parameters than similar published work. The presented power divider/combiner is very promising in power amplifier design by combining multiple power transistors in both RF board level and LTCC package level.